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, Mon, 21 Mar 2005 05:44:21
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The Dueling Article Game:
The primary fallacy of the "RISC and CISC have converged" school of thought is to ignore the distinction between an instruction set architecture (ISA) and the internal microarchitecture of an actual processor implementation. RISC and CISC refer to ISAs, which are abstract models of computer architectures as seen by the programmer. An ISA includes the programmer and compiler visible state of a computer, including all registers and flags, the encoding and semantics of all instructions, exception handling, and memory organization and semantics (little-endian vs big-endian, weakly-ordered vs strongly-ordered). An ISA does not tell computer engineers how an implementation must be realized......
The proponents and popularizers of the "RISC and CISC have converged" school of thought are so caught up in comparing chip organization and micro-architecture that they miss the big picture. The benefit of RISC ISA-based processor design comes in two separate packages. They focus on the first package: the ease of design of simplified and fast hardware. The era of 10 and 15 million transistor chips with three and four way superscalar issue and out-of-order execution has somewhat reduced (but not eliminated) this benefit, because in a sense all these chips, RISC and CISC alike, are damn complicated!.......
But the second benefit of RISC is the computational model - the ISA - it offers to the compiler. A RISC ISA offers a streamlined and simplified instruction set, and a generous set of general purpose registers. Most RISC designs do away with condition codes and instead rely on either storing Boolean control information in general purpose registers, atomically combining comparison and branch operations in single instructions, or a combination of both. In Figure 2 are the programmer's visible register resources of the x86 and Alpha ISAs. The bottom line is that the x86 has 8 general purpose integer registers, while RISC processors have 32. Ironically, both modern x86 and RISC processors have even far more physical data registers in them than shown here to accomplish register renaming, a powerful design tool used to eliminate the effect of false dependencies between instructions that would otherwise prevent out-of-order execution. However, it is the computational model seen by the compiler that is critical for the generation of ultra fast code......
The modern compiler is, in many ways, as complex and fascinating as the processors it creates code for. But the vital ingredient that allows a sophisticated compiler to excel is a large and unencumbered register set. A large register set facilitates such powerful optimization techniques as local and global variable register assignment, register-based parameter passing and function result return, and re-use of intermediate computational results from the calculation of common sub-expressions. In addition it is well known that because of loops, roughly 90% of program time is spent executing 10% of code. RISC ISAs, with their large register sets, support powerful loop-based optimizations such as array index address calculation strength reduction, software pipelining, and loop unrolling. Besides the large register sets, most RISC ISAs also incorporate three address instructions, that is, instructions that specify three registers - two source and one destination. The x86 and nearly every other CISC ISA use only one or two address instructions which means that extra move instructions are needed when it's necessary not to overwrite either of two operand registers.......
The "RISC and CISC are converging" viewpoint is a fundamentally flawed concept that goes back to the i486 launch in 1992 and is rooted in the widespread ignorance of the difference between instruction set architectures and details of physical processor implementation. Modern out-of-order execution x86 and RISC processors *do* have very similar organization in their back end execution engines, both of may which contain 40 or more physical renaming registers. While RISC data paths are driven directly by RISC instructions, x86 data paths are similarly driven by sequences of simple, shallowly encoded microcode-like control words called micro-ops, or provocatively, RISC-ops.
posted by 24.91.254...
, Mon, 21 Mar 2005 05:44:21, Mon, 21 Mar 2005 07:18:26, Tue, 22 Mar 2005 01:11:21, Mon, 21 Mar 2005 07:23:50
, Sun, 20 Mar 2005 21:33:11
, Mon, 21 Mar 2005 10:36:43, Mon, 21 Mar 2005 07:22:45, Tue, 22 Mar 2005 04:48:30
, Tue, 22 Mar 2005 17:27:08, Mon, 21 Mar 2005 11:54:07, Sun, 20 Mar 2005 21:02:09
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